FPGA Simulator · ATLAS Tile Calorimeter

HITS

Hardware Impulse Train Synthesizer

HITS is a real-time FPGA simulator of the ATLAS Tile Calorimeter readout. It runs at 40 MHz on a Terasic DE10-Nano and rebuilds the front-end signal chain in synthesizable Verilog: pseudo-random hits following the LHC bunch-train structure, energy amplitudes drawn from measured distributions, electronic noise, analog shaping and an embedded pole-zero cancellation. It lets the group validate online energy-reconstruction without access to the experiment.

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FPGA Verilog DE10-Nano · Cyclone V SoC ATLAS TileCal Open Source Active

A calorimeter readout, rebuilt in silicon

The real detector delivers one digitized sample every 25 nanoseconds, in step with the LHC bunch crossings. HITS produces that same stream on an FPGA: a hit either lands in a given crossing or it does not, and when it does, the pulse carries an energy drawn from the measured minimum-bias distribution, buried in electronic noise and shaped by the front-end electronics.

Because occupancy and pedestal can be changed at runtime from the board's ARM processor, the same hardware can stand in for quiet and busy beam conditions. That makes it a bench for testing energy-estimation and filtering algorithms long before they ever see real data.

Synthesized pulse train. Each pulse sits on a bunch crossing; its height is the energy amplitude drawn per hit, and the flat stretch is a quiet section of the LHC bunch train. This is the shape HITS writes out sample by sample.

The signal chain

The synthesizable core chains four blocks, one sample per clock cycle, ending at the digitized ADC value. Every block is plain Verilog with its lookup memories in .mif files.

1 RANDOMNESS

Random number generation

A bank of seven LFSRs with a selector produces uncorrelated pseudo-random streams that feed every stochastic step downstream.

rand_LFSR · select_rand · random_number_generator

2 HITS

Hit generation

A Bernoulli draw decides, per bunch crossing, whether a hit occurs. It is gated by the LHC bunch-train mask and the programmable occupancy.

Hits_Bunch_train · hits_positions · bunch_train_mask

3 ENERGY

Amplitude and noise

Inverse-CDF lookup, split across several memories, draws energy amplitudes from a measured distribution and adds Gaussian electronic noise.

energy_* + A13_PART*.mif · noise_* + NOISE_PART*.mif

4 SHAPING

Shaping and digitization

An IIR model of the front-end shaper, then pedestal offset and clipping to the ADC range. The output shaper_clip is the readout sample.

shaper_fenics · iir_order1 · iir_order2 · clip_shaper

Pole-zero cancellation (pzc_ped_track.v) is not part of the simulator. It is a downstream reconstruction stage, validated against the synthesized pulse train and composed with the core by the FPGA_Simulator_v1_PZC.v test wrapper. The board top wires that wrapper to the ARM processor through Qsys.

40 MHz

One sample every 25 ns, matching the LHC bunch-crossing clock

7 LFSRs

Uncorrelated pseudo-random streams behind every draw

Runtime

Occupancy and pedestal set live from the ARM processor

Bit-exact

A frozen golden VCD guards every change to the RTL

What is inside

Runtime occupancy and pedestal

Change beam conditions on the fly from the embedded HPS with ./change_occupancy over SSH. The effect is visible live in SignalTap.

Multi-memory inverse-CDF sampling

Energy and noise are sampled by looking up a measured distribution split across several on-chip memories, the approach published by the group for FPGA random generators.

FENICS shaper as an IIR filter

The analog front-end pulse shape is reproduced by first and second-order IIR sections, then offset by the pedestal and clipped to the ADC range.

Bit-exact regression

A frozen golden VCD and compare_vcd.py catch any unintended change. Deliberate changes regenerate the baseline in the same commit.

Runs with or without the board

The core is dependency-free Verilog, so it runs in open-source simulators as well as on the DE10-Nano. Same RTL, same output.

Run the simulation

projects/aurora

# plain Verilog, no board required
$ cd projects/aurora
$ iverilog -s sim_pulsos_tb -o tb.vvp \
      ../../rtl/*.v ../../rtl_test/*.v sim_pulsos_tb.v
$ vvp tb.vvp              # writes sim_pulsos_tb.vcd

# regression: exit 0 means bit-for-bit identical
$ python ../../verification/compare_vcd.py \
      sim_pulsos_tb.vcd

Or open projects/aurora/sim_pulsos.spf in AURORA and press the wave button. The testbench drives three full LHC orbits with an occupancy step halfway through, from Icarus Verilog straight into GTKWave.

On the DE10-Nano

Flash the prebuilt Linux SD-card image, set the MSEL switches to ON and power on: Linux boots and programs the FPGA for you. SSH in, run the occupancy menu, and watch the internal signals live in SignalTap.

See it running

GTKWave showing the simulated HITS pulse train — Simulation output, straight from the testbench.

SignalTap capture on the DE10-Nano board — The same signals, on real hardware.

Have a capture to add? Drop a PNG at the path shown and it replaces the placeholder automatically.

Published work

HITS grew out of the NIPS-CERN line on digital signal processing for the ATLAS Tile Calorimeter. The random generator, the signal-conditioning stage and the full simulator have each been described in peer-reviewed venues.

All publications

Multi-Memory Approach for Random Number Generators in FPGA

T. Paschoalin, L. Quirino, L. Andrade Filho

Applied Sciences 16(5) 2537 · 2026

Digital Implementation of a Signal Conditioning Stage on FPGA for Pulse Simulation in Nuclear Instrumentation

F. Luna, T. Paschoalin, L. Quirino, L. Andrade Filho

10th INSCIT · 2026

Uncorrelated Pseudo-Random Generator for FPGA

T. Paschoalin, A. Dias, M. Aguiar, V. Santos, L. Quirino, L. Andrade Filho

38th SBCCI · 2025

Real-time FPGA-based simulator for the Tile Calorimeter readout system in the ATLAS experiment

F. Luna, A. Dias, G. Lisboa, T. Paschoalin, L. Quirino, L. Andrade Filho

XXVII ENEMC · 2024

Get HITS

Clone the repository to simulate on your machine, or download the SD-card image to bring up the DE10-Nano. Everything is on GitHub under the NIPS-CERN License.

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