Implementação em FPGA de Transformada Wavelet para Compactação de Sinais Elétricos de Sistemas de Potência Utilizando Processador Embarcado

Abstract

This work aims to present an implementation of the Wavelet Transform on an FPGA (Field Programmable Gate Array). Using this tool, it is possible to achieve fast compression of electrical signals, either smoothing or enhancing their details. Additionally, the work compares this approach when implemented on an embedded processor with a direct implementation that uses multiple logic blocks, referred to as the parallel method. The comparison considers both the number of logic blocks required and the processing speed in each case. A prototype was developed to implement both methods, successfully achieving signal compression in which more than 85% of the samples, acquired at a rate of 7.68 kHz, could be replaced by zero while preserving over 99.9% of the original signal energy. The reconstruction error was limited to approximately 10⁻²%.