Implementação de Circuitos Aritméticos em Ponto Flutuante, Utilizando Formato com Número de Bits Configurável

Abstract

A representation of real numbers in binary systems led to the establishment of floating-point numeric representations. In addition to accurately representing numeric values, efficiently performing arithmetic operations—such as addition, multiplication, division, and subtraction—between floating-point numbers, with minimal error and fast response time, is a key requirement. Currently, the IEEE 754 standard is the most widely used representation in computational systems. This work presents a simplified floating-point representation implementation in which the number of bits is parameterizable. The implemented circuits rely solely on combinational logic, aiming to optimize operation response time while allowing the number of logic elements to be adjusted according to the target application.