Implementação em FPGA de um Método Recursivo de Deconvolução Aplicado em Calorímetros Operando a Alta Taxa de Eventos

Abstract

The LHC particle accelerator has undergone an update process, leading to the effect known as pile-up (overlapping signals) in the experiment front-end electronics. Since the algorithm currently used for reconstructing the energy generated in these collisions is not tolerant to this effect, this work proposes a hardware implementation of an iterative method based on a variant of Gradient Descent that recovers the amplitude information of superimposed signals within an acquisition window. With this implementation, dozens of channels can be processed in parallel within a single FPGA, while also meeting the required operating latency constraints of the ATLAS acquisition system.