Linear Equation System Solver Circuit for Streaming Processing in FPGA

Abstract

The solution of linear equation systems (LES) has numerous applications in digital signal processing. However, due to its high computational cost, implementing such solutions in high-speed, free-running (streaming) processing applications is challenging. This work presents an FPGA-based implementation of a digital circuit for solving LES using the gradient descent method, capable of operating online. This implementation introduces a new perspective for executing iterative, matrix-based algorithms in embedded systems designed for high-speed (tens of MHz) continuous data flow. In other words, the proposed method functions as a real-time processing block, where new data enters and processed data exits at each clock cycle, enabling seamless integration of matrix computations into continuous-flow systems. In addition to presenting the implementation architecture, this work analyzes the relationship between the number of iterations, resource utilization, and the achievable acquisition rate. As a case study, the method is applied to a channel equalization problem.