Design and Implementation of a Digital IIR Filter with Floating-Point Representation

Abstract

This paper presents the implementation of a digital IIR filter on an FPGA using floating-point operations to minimize errors caused by quantization. A fully combinational floating-point multiply-and-accumulate circuit is proposed, avoiding the use of pipeline stages typically required in conventional FPGA implementations. This architectural choice simplifies control, enables immediate output response, and is particularly advantageous in applications requiring low latency and predictable timing. In contrast, the quantization process in fixed-point designs is highly specific to each project and often demands extensive tuning and simulation, significantly increasing development time. By adopting floating-point arithmetic, the proposed method eliminates this overhead, offering greater flexibility and accelerating the design process, albeit at the cost of increased logic utilization. The implementation aims to reduce deviations from the ideal impulse response while maintaining filter stability and achieving high numerical accuracy with fewer bits. The results demonstrate the effectiveness of this approach compared to traditional quantization-based methods, particularly in scenarios where design time and precision are critical.