Real-Time FPGA-Based Pulse Simulator for the ATLAS Tile Calorimeter Readout Chain at the HL-LHC

Abstract

The LHC and the ATLAS experiment will undergo a Phase-II upgrade, imposing stringent requirements on real-time data processing. The Tile Calorimeter (TileCal) readout electronics will be fully replaced, and the digitised samples of every channel will be streamed continuously at the LHC bunch-crossing frequency of 40.08 MHz to off-detector FPGAs, where the deposited energy is reconstructed online. Developing, validating and testing the firmware that performs this reconstruction calls for a real-time FPGA-based simulator of the TileCal readout chain, which has been built for this purpose. It generates, at every bunch crossing, the energy deposited in a selected calorimeter cell according to its statistical distribution, adds realistic electronic noise, reproduces the response of the FENICS front-end shaper by means of an IIR filter, and emulates the 12-bit ADC of the upgraded electronics. Implemented on a Kintex UltraScale device, it uses about 1% of the available logic and closes timing with about 3% of margin over the bunch-crossing frequency. This enables systematic validation, stress testing and performance evaluation of hardware-based trigger and energy reconstruction firmware under realistic and repeatable conditions.