Digital Implementation of a Signal Conditioning Stage on FPGA for Pulse Simulation in Nuclear Instrumentation

Abstract

In nuclear instrumentation, accurate pulse processing is essential for extracting meaningful information from detector signals. However, developing and validating processing techniques directly on experimental setups is often impractical due to high costs, restricted access, and radiation exposure constraints. Real-time pulse simulators provide a controlled alternative for evaluating signal reconstruction algorithms. A critical component of such simulators is the signal conditioning stage (shaper), whose long-tail impulse response must be faithfully reproduced to capture pile-up and baseline shift effects. While FIR filters are commonly used for digital pulse shaping, they cannot efficiently represent slowly decaying responses, requiring an impractical number of coefficients. This work proposes an IIR-based digital shaper implemented on FPGA, obtained by discretizing the analog transfer function using the Impulse Invariant Method and decomposing it into parallel first- and second-order sections described with fixed-point arithmetic. Validation against an ideal reference confirmed minimal quantization error, and the implementation successfully reproduced the long-tail behavior and baseline shift characteristic of the analog circuit. The resource utilization remained below one percent on the target device, indicating that the proposed shaper can be integrated with other signal reconstruction modules without compromising the FPGA capacity available for additional processing stages.