Multi-Memory Approach for Random Number Generators in FPGA

Abstract

Random number generation is essential in many application domains, including high-energy physics simulations. Implementing Monte Carlo methods that generate samples according to a desired probability distribution is particularly challenging on hardware platforms such as FPGAs. Direct implementations of analytical distribution functions are often resource-intensive, making them impractical for real-time systems. An efficient alternative is the use of the inverse cumulative distribution function (CDF), which can be implemented using look-up tables (LUTs). In this approach, a uniformly distributed random number—generated by linear feedback shift registers (LFSRs)—is used as an address to access LUTs containing discretized values of the CDF, thereby producing the desired random variable. However, this method presents limited accuracy in low-probability regions of the distribution. To address this limitation, this paper proposes a segmented CDF implementation based on multiple LUTs, improving resolution in poorly sampled regions. A cascade of decision logic is used to select the appropriate memory output, increasing resolution only where necessary while optimizing memory usage. The proposed method is validated through Monte Carlo simulations in particle physics applications, showing close agreement with theoretical distributions while requiring low FPGA resource utilization and no DSP blocks.