SAPHO

The whole trick is one instantiation: each instruction your program uses becomes a Verilog parameter set to 1, and each block sits behind a generate if on it. Not used, not built. Pick a program; the dotted tokens are the ones that become hardware, so point at one.

while (1)
{
    x[3] = x[2];              // shift the history
    x[2] = x[1];
    x[1] = x[0];
    x[0] = in(0);             // new sample

    soma = x[0] + x[1] + x[2] + x[3];
    out(0, soma >> 2);    // mean, no divider
}

processor #(
    .NUBITS(16), .NBMANT(10), .NBEXPO(5),
    .LOD(1), .SET(1), .INN(1), .OUT(1),
    .JMP(1), .JIZ(1), .ADD(1), .SHR(1)
    // every other instruction stays 0
) u_proc ( /* ... */ );

FIG. 1 One button runs the chain: cmmcomp → appcomp → asmcomp → .v + .mif + testbench; the TASM terminal prints this same inventory on every build. The chain in detail · See it as a circuit, in PRISM

A SAPHO simulation carries two extra tracks: the assembly instruction retiring on each clock, and the C± line it came from. One turn of the filter loop below; run it, or drag across.

FIG. 2 In the IDE the tracks are decoded straight from the build, for any program, with your variables shown by name. How the tracks work · Waves, viewers and layouts

AURORA is the desktop IDE of the platform: editor, compilers, two simulators, two waveform viewers and the circuit diagram, no cloud behind any of it.

FIG. 3 · AURORA.EXEmain window

FIG. 4 · PRISMRTL view

FIG. 5 · EDITORC± source

FIG. 6 · WAVEStwo viewers

These are the actual tools that ship, each doing the job it is best at.

01AURORAthe IDE, one window for the whole flow 02YANCthe compilers: cmmcomp, appcomp, asmcomp 03C±the language your processor is drawn from 04Icarus Verilogsimulation, every signal visible 05Verilatorfast simulation for long runs 06GTKWavewaveform viewer, the classic 07Surferwaveform viewer, our fork 08YosysRTL analysis behind the diagram 09PRISMthe circuit diagram, hierarchy and all 10cocotbtestbenches in Python