SAPHO
Scalable-Architecture Processor for Hardware Optimization
SAPHO is a scalable hardware architecture and integrated toolchain for processor creation, experimentation, and hardware–software co-design — designed to make custom processor development accessible from university classrooms to research labs.
What SAPHO Includes
SAPHO provides an end-to-end environment for processor design: from writing high-level CMM code to compiling, simulating, and visualising the resulting hardware. It bundles four major components — YANC, AURORA, Surfer, and PRISM — into a single cohesive installer.
The architecture is designed around a custom processor model that students and researchers can modify freely. SAPHO runs identically on Windows and Linux, and the entire compilation pipeline — from source to machine code — executes without any cloud dependency.
The SAPHO Ecosystem
From the Lab to the Classroom
SAPHO is being implemented as the core platform for the DLP (Dispositivos Lógicos Programáveis — Programmable Logic Devices) discipline at UFJF — Universidade Federal de Juiz de Fora. Every student enrolled in this course designs, compiles, and simulates custom processor architectures using SAPHO.
This means NIPS-CERN is directly shaping the next generation of hardware engineers graduating from UFJF. SAPHO bridges the gap between theoretical computer architecture concepts and hands-on hardware design experience.
All students who take or will take the DLP discipline at UFJF work with our custom processor. NIPS-CERN is forming a generation of engineers on our own platform, with our own tools, built in-house.
What Students Do with SAPHO
Technical Architecture
SAPHO's design separates compilation, simulation, and visualisation into dedicated components, each independently usable yet tightly integrated through the AURORA IDE.
YANC bridges the gap between high-level description and machine execution. It includes cmmcomp (CMM → assembly), asmcomp (assembly → binary/hex), and APP auxiliary tools.
AURORA is the desktop IDE for SAPHO. It embeds Monaco Editor (the engine behind VS Code) for code, runs Icarus Verilog and Verilator simulations, and brings compilation, waveform inspection and the PRISM RTL viewer into one window. Aurora Intelligence adds an AI assistant that drives the IDE through its own tools.
Surfer is a fast, open-source waveform viewer. The group maintains a fork of it wired into AURORA, so inspecting signal timelines, register states, and data flows over clock cycles happens without switching tools.
PRISM renders processor structure and datapaths as RTL diagrams, making it straightforward to understand and debug the hardware description. Students can visually trace how data moves through their processor design.
Download SAPHO
Download the latest SAPHO installer for Windows or Linux from the official GitHub Releases page. The installer bundles YANC, AURORA, Surfer, and PRISM into a single setup.